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HDD32M64B8
DDR SDRAM Module 256Mbyte (32Mx64bit), based on32Mx8,4Banks, 8K Ref., SO-DIMM Part No. HDD32M64B8
GENERAL DESCRIPTION
The HDD32M64B8 is a 32M x 64 bit Double Data Rate(DDR) Synchronous Dynamic RAM high-density memory module. The module consists of eight CMOS 32M x 8 bit with 4banks DDR SDRAMs in 66pin TSOP-II 400mil packages and 2K EEPROM in 8-pin TSSOP package on a 200-pin glass-epoxy. Four 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each DDR SDRAM. The HDD32M64B8 is a SO-DIMM(Small Outline Dual in line Memory Module) .Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable latencies and burst lengths allows the same device to be useful for a variety of high bandwidth, high performance memory system applications. All module components may be powered from a single 2.5V DC power supply and all inputs and outputs are SSTL_2 compatible.
FEATURES
* Part Identification HDD32M64B8 - 10A : HDD32M64B8 - 13A : HDD32M64B8 - 13B : 100MHz (CL=2) 133MHz (CL=2) 133MHz (CL=2.5)
* 256MB(32Mx64) Unbuffered DDR SO-DIMM based on 32Mx8 DDR SDRSM * 2.5V 0.2V VDD and VDDQ power supply * Auto & self refresh capability (8192 Cycles/64ms) * All input and output are compatible with SSTL_2 interface * Data(DQ), Data strobes and write masks latched on the rising and falling edges of the clock * All Addresses and control inputs except Data(DQ), Data strobes and Data masks latched on the rising edges of the clock * MRS cycle with address key programs - Latency (Access from column address) : 2, 2.5 - Burst length : 2, 4, 8 - Data scramble : Sequential & Interleave * Data(DQ), Data strobes and write masks latched on the rising and falling edges of the clock * All Addresses and control inputs except Data(DQ), Data strobes and Data masks latched on the rising edges of the clock * The used device is 8M x 8bit x 4Banks DDR SDRAM
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PIN ASSIGNMENT
PIN 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 Front VREF VSS DQ0 DQ1 VDD DQS0 DQ2 VSS DQ3 DQ8 VDD DQ9 DQS1 VSS DQ10 DQ11 VDD CK0 /CK0 VSS DQ16 DQ17 VDD DQS2 DQ18 VSS DQ19 DQ24 VDD DQ25 DQS3 VSS DQ26 PIN 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 Back VREF VSS DQ4 DQ5 VDD DM0 DQ6 VSS DQ7 DQ12 VDD DQ13 DM1 VSS DQ14 DQ15 VDD VDD VSS VSS DQ20 DQ21 VDD DM2 DQ22 VSS DQ23 DQ28 VDD DQ29 DM3 VSS DQ30 PIN 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 Frontl DQ27 VDD NC NC Vss NC NC VDD NC NC VSS CK2 /CK2 VDD CKE1 NC(A13) A12 A9 VSS A7 A5 A3 A1 VDD A10/AP BA0 /WE /CS0 NC VSS DQ32 DQ33 VDD PIN 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 Back DQ31 VDD NC NC Vss NC NC VDD NC NC(/RESET) VSS VSS VDD VDD CKE0 NC (BA2) A11 A8 VSS A6 A4 A2 A0 VDD BA1 /RAS /CAS NC NC VSS DQ36 DQ37 VDD PIN 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 *These pins should be NC in the system which does not support SPD PIN PIN DESCRIPTION PIN A0~A12 BA0~BA1 DQ0~DQ63 DQS0~DQS7 DM0~DM7 CK0~CK2,/CK0~/CK2 CKE0~CKE1 /CS0 /RAS, /CAS NC
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HDD32M64B8
Front DQS4 DQ34 VSS DQ35 DQ40 VDD DQ41 DQS5 VSS DQ42 DQ43 VDD VDD VSS VSS DQ48 DQ49 VDD DQS6 DQ50 VSS DQ51 DQ56 VDD DQ57 DQS7 VSS DQ58 DQ59 VDD *SDA *SCL *VSPD VDDID
PIN 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200
Back DM4 DQ38 VSS DQ39 DQ44 VDD DQ45 DM5 VSS DQ46 DQ47 VDD /CK1 CK1 VSS DQ52 DQ53 VDD DM6 DQ54 VSS DQ55 DQ60 VDD DQ61 DM7 VSS DQ62 DQ63 VDD *SA0 *SA1 *SA2 NC
PIN DESCRIPTION Power supply(2.5V) Power supply for DQs(2.5V) Power supply for reference Serial EEPROM Power supply(3.3) Ground Address in EEPROM Serial data I/O Serial clock Write protection VDD identification flag
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Address input Bank Select Address Data input/output Data Strobe input/output Data-in Mask Clock input Clock enable input Chip Select input Row / Column Address strobe No connection
2
VDD VDDQ VREF VSPD VSS SA0~SA2 SDA SCL WP VDDID
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FUNCTIONAL BLOCK DIAGRAM
/CS0
HDD32M64B8
VSPD A12
A11
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PIN FUNCTION DESCRIPTION
Pin CK, /CK Clock Name
HDD32M64B8
Input Function CK and CK are differential clock inputs. All address and control input signals are sam-pled on the positive edge of CK and negative edge of CK. Output (read) data is referenced to both edges of CK. Internal clock signals are derived from CK/CK. CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN(row ACTIVE in any bank). CKE is synchronous for all functions
CKE
Clock Enable
except for disabling outputs, which is achieved asynchronously. Input buffers, excluding CK, CK and CKE are disabled during power-down and self refresh modes, providing low standby power. CKE will recognizean LVCMOS LOW level prior to VREF being stable on power-up. CS enables(registered LOW) and disables(registered HIGH) the command decoder. All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. Row/column addresses are multiplexed on the same pins.
/CS
Chip Select
A0 ~ A12
Address
Row address : RA0 ~ RA12, Column address : CA0 ~ CA9 BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRE-CHARGE
BA0 ~ BA1
Bank select address
command is being applied. Latches row addresses on the positive going edge of the CLK with /RAS low.
/RAS
Row address strobe Column strobe Write enable address
Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with /CAS low. Enables column access. Enables write operation and row precharge.
/CAS
/WE
Latches data in starting from /CAS, /WE active. Output with read data, input with write data. Edge-aligned with read data, cen-
DQS0 ~ 7
Data Strobe
tered in write data. Used to capture write data. DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled
DM0~7
Input Data Mask
on both edges of DQS. DM pins include dummy loading internally, to matches the DQ and DQS load-ing.
DQ0 ~ 63 VDDQ VDD VSS
Data input/output Supply Supply Supply
Data inputs/outputs are multiplexed on the same pins. DQ Power Supply : +2.5V 0.2V. Power Supply : +2.5V 0.2V (device specific). DQ Ground.
VREF VSPD VDDID
Supply Supply
SSTL_2 reference voltage. Serial EEPROM Power Supply : 3.3v VDD identification Flag
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ABSOLUTE MAXIMUM RATINGS
PARAMETER Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Voltage on VDDQ supply relative to Vss Storage temperature Power dissipation SYMBOL VIN, VOUT VDD VDDQ TSTG PD RATING -0.5 ~ 3.6 -1.0 ~ 3.6 -0.5 ~ 3.6 -55 ~ +150 8.0
HDD32M64B8
UNTE V V V C W mA
Short circuit current IOS 50 Notes: Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITIONS
(Recommended operating conditions (Voltage referenced to Vss = 0V, TA = 0 to 70C) )
PARAMETER SYMBO L Supply Voltage I/O Supply Voltage I/O Reference Voltage I/O Termination Voltage(system) Input High Voltage Input Low Voltage Input Voltage Level, CK and /CK inputs Input Differential Voltage, CK and /CK inputs Input leakage current Output leakage current Output High current (VOUT = 1.95V) VDD VDDQ VREF VTT VIH (DC) VIL (DC) VIN (DC) VID (DC) I LI I OZ I OH 2.3 2.3 VDDQ/2-50mV VREF - 0.04 VREF + 0.15 -0.3 -0.3 0.3 -2 -5 -16.8 2.7 2.7 VDDQ/2+50mV VREF + 0.04 VREF + 0.3 VREF - 0.15 VDDQ + 0.3 VDDQ + 0.6 2 5 V V V V V V V V uA uA mA mA 3 1 2 MIN MAX UNIT NOTE
Output Low current (VOUT = 0.35V) I OL 16.8 Notes : 1. Typically, the value of VREF is expected to be about 0.5* VDD of the transmitting device. VREF is expected to track variation in VDDQ . 2. Peak to peak AC noise on VREF may not exceed 2% VREF (DC). 3. VTT of the transmitting device must track VREF of the receiving device.
CAPACITANCE
(VDD = min to max, VDDQ = 2.5V to 2.7V, TA = 25C, f = 100MHz)
DESCRIPTION SYMBOL CIN1 CIN2 CIN3 CIN4 CIN5 COUT1
5
MIN 36 36 34 34 8 8
MAX 44 44 42 38 9 9
UNITS pF pF pF pF pF pF
Input capacitance(A0~A12, BA0~BA1, /RAS, /CAS,/WE) Input capacitance(CKE0,CKE1) Input capacitance(/CS0) Input capacitance(CK0~CK2, /CK0~/CK2) Input capacitance(DM0~DM7) Data input/output capacitance (DQ0 ~ DQ63, DQS0~DQS7)
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DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, VDD = 2.5V, T =25C)
SYMBO PARAMETER L CONDITION Burst length = 2 Operating current IDD1 (One bank active) tRC tRC(min), CL=2.5 IOUT = 0mA, Active-Read-Presharge CKE VIL(max) IDD2P tCK = tCK(min), All banks idle standby IDD2N CKE VIH(min) /CS VIH(min), tCK(min) 160 200 800 960 -10A -13A TEST VERSION
HDD32M64B8
UNIT -13B
NOTE
960
mA
Precharge standby current in power-down mode Precharge current in non power-down mode Active standby current in IDD3P power-down mode Active standby current in non power-down mode (One bank active) Operating current IDD4R (Read) IDD3N
200
mA
tCK
=
280
320
320
mA
All banks idle, CKE VIL(max), tCK = tCK(min) Onel banks, Active-Read-Presharge, tRC=tRAS(max), tCK tCK(min) Burst length = 2 tRC = tRC(min), IOUT = 0mA,
280
320
320
mA
=
360
440
440
mA
CL=2. 5 CL=2 CL=2. 1200 1440 1440 mA
Operating current IDD4W (Write) Auto refresh current Self refresh Normal IDD6 IDD5
Burst length = 2 5 tRC = tRC(min) CL=2 tRC tREF(min) CKE 0.2V 1200 24 1440 24 1440 24 12 mA mA mA 1520 1920 1920 mA
current Low Power 12 12 Notes: Operation at above absolute maximum rating can adversely affect device reliability
AC OPERATING CONDITIONS
PARAMETER
Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals. Input Differential Voltage, CK and CK inputs Input Crossing Point Voltage, CK and CK inputs STMBOL VIH (AC) VIL (AC) VID (AC) VIX (AC) 0.7 0.5*VDDQ-0.2
MIN
VREF + 0.35
MAX
UNIT
NOTE
VREF - 0.31 VDDQ+0.6 0.5*VDDQ+0.2
V V V 1 2
Notes: 1. VID is the magnitude of the difference between the input level on CK and the input on CK. 2. The value of VIX is expected to equal 0.5* VDDQ of the transmitting device and must track variations in the DC level of the same
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AC OPERATING TEST CONDITIONS
PARAMETER Input reference voltage for Clock Input signal maximum peak swing Input signal minimum slew rate Input Levels(VIH/VIL) Input timing measurement reference level Output timing measurement reference level Output load condition VALUE 0.5 * VDDQ 1.5 VREF+0.31/VREF-0.31 VREF+0.35/VREF VREF VTT See Load Circuit
HDD32M64B8
UNIT V V V V V V V
NOTE
AC CHARACTERISTICS (These AC charicteristics were tested on the Component)
DDR200 SYMBO PARAMETER L Row cycle time Refresh row cycle time Row active time /RAS to /CAS delay Row precharge time Row active to Row active delay Write recovery time Last data in to Read command Col. address to Col. address delay CL=2.0 Clock cycle time CL=2.5 Clock high level width
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DDR266A -13A
DDR266B -13B MIN 65 75 MAX ns ns 120K ns ns ns ns tCK tCK tCK 12 12 0.55 ns ns tCK 1 1,2 1,2 3 3 3 3 2 UNIT NOTE
-10A MIN 70 80 48 20 20 15 2 1 1 10 12 12 120K MAX
MIN 65 75 45 20 20 15 2 1 1 7.5 7.5 0.45
MAX
tRC tRFC tRAS tRCD tRP tRRD tWR tCDLR tCCD tCK
120K
45 20 20 15 2 1 1
12 12 0.55
10 7.5 0.45
tCH
0.45
7
0.55
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Clock low level width DQS-out access time from CK/CK tDQSCK Output data access time from CK/CK tAC Data strobe edge to ouput data edge Read Preamble Read Postamble Data out high impedence time from CKtHZQ /CK CK to valid DQS-in DQS-in setup time DQS-in hold time DQS-in falling edge to CK rising-setup tDSS time DQS-in falling edge to CK rising hold tDSH time DQS-in high level width DQS-in low level width DQS-in cycle time Address and Control Input setup time Address and Control Input hold time Mode register set cycle time DQ & DM setup time to DQS DQ & DM hold time to DQS DQ & DM input pulse width Power down exit time Exit self refresh to write command Exit self refresh to bank active tXSA command Exit self refresh to read command Refresh interval time Output DQS valid window DQS write postamble time Notes : 1. 2. Maximum burst refresh of 8. tXSR TREF TQH TWPST 200 15.6 tHPmin -tQHS 0.25 200 15.6 tHPmi n -tQHS 0.25 200 15.6 tHPmin -tQHS 0.25 80 tDQSH tDQSL tDSC tIS tIH tMRD tDS tDH tDIPW tPDEX tXSW 0.35 0.35 0.9 1.1 1.1 16 0.6 0.6 2 10 116 1.1 0.35 0.35 0.9 0.9 0.9 15 0.5 0.5 1.75 10 95 75 75 1.1 0.35 0.35 0.9 0.9 0.9 15 0.5 0.5 1.75 10 0.2 0.2 0.2 0.2 0.2 0.2 tDQSS tWPRES tWPREH 0.75 0 0.25 1.25 0.75 0 0.25 1.25 0.75 0 0.25 -0.8 +0.8 -0.75 +0.75 -0.75 tDQSQ tRPRE tRPST -0.8 0.9 0.4 +0.8 +0.6 1.1 0.6 -0.75 0.9 0.4 +0.75 +0.5 1.1 0.6 -0.75 -0.8 +0.8 -0.75 +0.75 -0.75 tCL 0.45 0.55 0.45 0.55 0.45
HDD32M64B8
0.55 +0.7 ns 5 +0.7 ns 5 0.9 0.4 +0.5 1.1 0.6 +0.7 ns 5 1.25 tCK ns tCK tCK 3 2 ns tCK tCK tCK
tCK tCK tCK 1.1 tCK ns ns ns ns ns ns ns ns ns Cycle us tCK tCK 4 1
tHZQ transitions occurs in the same assess time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving.
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3.
HDD32M64B8
The specific requirement is that DQS be valid(High-Low) on or before this CK edge. The case shown(DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress, DQS could be High at this time, depending on tDQSS.
4.
The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter, but system performance (bus turnaround) will degrade accordingly.
SIMPLIFIED TRUTH TABLE
COMMAND Register Register Extended MRS Mode register set Auto refresh Refresh Self refresh Entry Exit CK E n-1 H H H L H precharge H precharge precharge H X L H L L H Bank selection All banks Entry Exit Entry Exit H H L H L H H X H L X X L H L H L L H L X H L H L H L X V X X H X V X X H X H X H H H X V X X H X V L L X V X X H X V X X X X X X X V X X X 8 V X L H X X L H L H X V CK E n X X H L H X /CS L L L L H L /R A S L L L H X L /C A S L L L H X H /WE L L H H X H DM X X X X X V BA 0,1 A10/ AP OP code OP code X X Row address L H H X V H X X L Column Address (A0 ~A9) Column Address (A0 ~ A9) 4,6 7 5 4 4 4 A11 A9~A0 NOTE 1,2 1,2 3 3 3 3
Bank active & row addr. Read & column address Write & column address Burst Stop Precharg e Auto disable Auto precharge eable Auto disable Auto enable
Clock suspend or active power down
Precharge power down mode DM
No operation command
(V=Valid, X=Don't care, H=Logic high, L=Logic low) Notes : 1. OP Code : Operand code A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state.
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4.
HDD32M64B8
5. 6. 7.
BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. Burst stop command is valid at every burst length. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0)
PACKAGING INFORMATION
Unit : mm
Front - Side
PCB
: 1.0 0.1mm
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ORDERING INFORMATION
HDD32M64B8
Part Number
Density
Org.
Package 200PIN SO-DIMM 200PIN SO-DIMM 200PIN SO-DIMM
Ref.
Vcc
MODE
MAX.frq
HDD32M64B8-10A HDD32M64B8-13A HDD32M64B8-13B
256MByte 256MByte 256MByte
32M x 64 32M x 64 32M x 64
8K 8K 8K
2.5V 2.5V 2.5V
DDR DDR DDR
100MHz/CL2 133MHz/CL2 133MHz/CL2.5
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